1. Field of the Invention
The present invention relates generally to a semiconductor device manufacturing technology, and particularly to a method for forming shallow trench isolation in a semiconductor device.
2. Description of the Related Art
Manufacturing processes for making a highly integrated semiconductor device requires forming a variety of components, such as a transistor, capacitor, metal wiring, etc., in very restricted regions, and forming highly insulated regions to prevent parasitic current leakage between the components.
Conventionally, a local oxidation of silicon (LOCOS) field oxide, formed by oxidizing a silicon substrate, has been widely used for electrically isolating the components of the semiconductor device. However, according to the increase of the integration density, a LOCOS field oxide has become disadvantageous to the formation of integrated circuits, because it generally includes a “bird's beak,” which may invade an active device region. Accordingly, a lot of alternative isolation technologies, more advantageous to the higher integration of devices, have been developed. As a typical example of such alternative isolation technologies, shallow trench isolation (STI) having a superior insulating performance and a relatively small formation area has been widely used for isolating transistors in metal oxide semiconductor field effect transistor (MOSFET) and bipolar junction transistor devices, since approximately the 0.5 micrometer (μm) technology node.
Hereinafter, a conventional STI process will be described with reference to FIG. 1.
First, a pad oxide 22 and a pad nitride 24 are formed on a silicon substrate 10 in successive order, then a moat pattern is formed thereon by photolithography and etching processes. The pad nitride 24 and the pad oxide 22 are partially etched in successive order, using the moat pattern as an etching mask. Subsequently, exposed portions of the substrate 10 are etched in a predetermined depth so that trenches 20 are formed around an active device area.
After the trench etch, a liner oxide (not shown) can be formed in each trench 20 to protect a trench sidewall, i.e., an inside surface of the silicon substrate 10 exposed by trench 20. Then, trenches 20 are filled with a filling oxide 20a. Here, the filling oxide 20a can be deposited by chemical vapor deposition (CVD) using O3-TEOS (Tetra Ethyl Ortho Silicate) oxidation film or high-density plasma chemical vapor deposition (HDP-CVD). Next, the substrate 10 is planarized via chemical and mechanical polishing (CMP) so that the filling oxide covering the active device area is selectively removed for device processing to continue. Finally, the pad nitride 24 and pad oxide 22 are removed by wet etching, thus resulting in a highly planar substrate with isolated device regions.
Referring to FIG. 1, even though O3-TEOS CVD or HDP-CVD having a relatively superior gap-filling ability is used, the filling oxide 20a inside trenches 20 can include voids 21a or seams 21b. The voids 21a and seams 21b can produce or result in problems such as a gate line bridge, etc., because they can emerge during CMP and wet etching processes. As a result, the voids 21a and seams 21b may deteriorate the insulating performance of the STI. In order to solve such problems, it can be considered to decrease a slope of the trench 20 or remove the pad nitride 24 in a predetermined width before formation of the filling oxide.
However, in case the width of the trench 20 is considerably narrow, especially in the sub-90 nanometer (nm) technologies, there is the limit of decreasing the slope of the trench 20. Excessive decreasing of the slope of trench 20 may result in defects (e.g., dislocations) in the silicon substrate 10, thus deteriorating the yield of semiconductor devices. In addition, the widening of the width of the trench entrance by removing a portion of the pad nitride 24 may result in problems where the active device region is decreased and a remaining portion of the pad nitride 24 peels off during the wet etching.